1. Field of the Invention
The invention relates generally to a method of forming a copper metal line in a semiconductor device. More particularly, the invention relates to a method of forming a copper metal line in a semiconductor device capable of preventing void that occurs within a via hole upon a process of forming a copper electroplating film to prohibit lowering in the yield of the via hole, and preventing damage of an underlying conductive material and a lower layer that occurs upon a process of forming a trench due to misalignment of the via hole and a conductive region.
2. Description of the Prior Art
Generally, in a semiconductor device, electron devices, or the like, a technology in which a conductive film such as aluminum (Al), tungsten (W), or the like is deposited on an insulating film and the conductive film is then patterned by common photolithography process and dry etching process to form a line, has been widely employed as a technology for forming the line. In particular, as an effort to reduce a RC delay time in a logic device of the semiconductor device that requires a high speed, a research on the use of a metal such as copper (Cu) having a low resistivity as the line instead of aluminum (Al) or tungsten (W) has recently been made.
In the process of forming the line using copper (Cu), however, as the patterning process of Cu is difficult compared to those of Al or W, a process by which a trench is formed and the trench is then buried to form the line, so called a damascene process has been used. The damascene process can be classified into a single damascene process by which a via hole is formed, the via hole is filled with a via conductive material and the trench for the line is then formed to bury the line, and a dual damascene process by which the via hole and the trench are formed and the via hole and the trench for the line are simultaneously filled with a material for the line. In general, in view of simplification of the process, the dual damascene process is better than the single damascene process.
The dual damascene process can be classified into a pre-via mode in which the via hole is first formed and the trench is then formed, and a post-via mode in which the trench for the line is first formed and the via hole is then formed. Generally, it has been known that the pre-via mode is better than the post-via mode in view of secure connection with the lower layer. A method of forming the copper metal line using the conventional dual damascene process of the pre-via mode will be described by reference to FIG. 3A through FIG. 3E.
Referring now to FIG. 3A, a first etch stop layer 306 that will serve as an etch stop layer in a subsequent process of forming a via hole is formed on a given lower layer 302 including a conductive region 304 using a SiN film, etc. Next, a first interlayer insulating film 308 is formed on the first etch stop layer 306 using silicon oxide having a low dielectric characteristic. A second etch stop layer 310 that will serve as the etch stop layer in a process of forming a trench for a line is then formed.
Thereafter, a second interlayer insulating film 312 is formed on the second etch stop layer 310 using silicon oxide having a low dielectric constant. Next, an insulating anti-reflecting film 314 that will have an anti-reflecting function in a subsequent process of patterning a photoresist is formed.
By reference to FIG. 3B, a photoresist (not shown) is formed on the entire structure. An exposure process and a development process are sequentially performed to form a photoresist pattern PR1 for the via hole.
Next, the anti-reflecting film 314, the second interlayer insulating film 312, the second etch stop layer 310 and the first interlayer insulating film 308 are anisotropically etched using the photoresist pattern PR1 as an etch mask, thus forming the via hole 316. At this time, a portion of the first etch stop layer 306 is etched. Further, all the first etch stop layer 306 may be etched, for necessary. Then, the photoresist pattern PR1 is removed by a strip process.
Referring to FIG. 3C, a photoresist (not shown) is formed on the entire structure. An exposure process and a development process are sequentially performed to form a photoresist pattern PR2 for the trench.
Next, the anti-reflecting film 314 and the second interlayer insulating film 312 are etched using the photoresist pattern PR2 as an etch mask, thus forming the trench 318. At this time, a portion of the second etch stop layer 310 is etched. Also, all the first etch stop layer 306 may be etched, for necessary. Then, the photoresist pattern PR2 is removed a strip process, for example by ashing using oxygen plasma.
Referring to FIG. 3D, a barrier layer 320 is formed using Ti, TiN, Ta or TaN on the entire structure including inner surfaces (i.e., including inner surfaces and bottom) of the via hole 316 and the trench 318.
Thereafter, a copper electroplating film 322 is formed to bury the via hole 316 and the trench 318. Before the copper electroplating film 322 is formed, a copper seed layer (not shown) is formed on the barrier layer 320.
By reference to FIG. 3E, an annealing process is performed in order to crystallize the copper electroplating film 322. A chemical mechanical polishing (CMP) process is then performed to remove the anti-reflecting film 314, the barrier layer 320, the seed layer and the electroplating film 322 formed on the second interlayer insulating film 312, thus forming a copper metal line 324.
However, the method of forming the copper metal line mentioned above, has some problems. In concrete, as shown in FIG. 4, thermal stress applied to the copper metal line is significantly varied depending on variation in the temperature. In particular, if the temperature is higher, thermal stress is significantly increased. Accordingly, void (see portion xe2x80x98Axe2x80x99 in FIG. 5A and FIG. 5B) is formed between the copper metal line 324 and the conductive region 304 due to hillock by thermal stress applied in the subsequent high-temperature annealing process, as shown in FIG. 5A and FIG. 5B. Further, as shown in FIG. 6, if misalignment (see portion xe2x80x98Bxe2x80x99) is generated in the process of forming the via hole 316 (see FIG. 3B), the lower layer 302 is over etched and a portion of the conductive material of the conductive region 304, for example, the thin copper film is over etched, in the subsequent process of forming the trench 318 (see FIG. 3C). Due to this, there is a problem that copper (Cu) ions are re-sputtered on the inner surface of the via hole 316.
The present invention is contrived to solve the above problems and an object of the present invention is to prevent void generating within a via hole in the process of forming a copper electroplating film and thus prohibit lowering in the yield of the via hole.
Another object of the present invention is to prevent damage of an underlying conductive material and a lower layer occurring in the process of forming a trench, due to misalignment of the via hole and a conductive region.
Still another object of the present invention is to prevent atoms of a conductive material from being re-sputtered on the inner surface of the via hole by damage of the conductive material in the process of forming the trench, due to misalignment of the via hole and the conductive region.
Further still another object of the present invention is to prohibit lowering in the yield of the via hole and also improve the yield of the copper metal line by preventing diffusion of Cu atoms.
In order to accomplish the above object, the method of forming the copper metal line according to the present invention, is characterized in that it comprises the steps of forming a first interlayer insulating film on a semiconductor substrate in which a lower layer is formed, forming an etch stop layer on the first interlayer insulating film, etching the etch stop layer and the first interlayer insulating film to form a via hole, forming a via plug to bury the via hole, forming a buffer film covering the via plug in order to buffer a stress applied in a subsequent process, forming a second interlayer insulating film on the entire structure, etching the second interlayer insulating film to form a trench through which the buffer film is exposed, and forming a copper metal line to bury the trench.